Generally most electronic devices are equipped with a form of error detection and error correction. For example, most DVD players, wireless devices, flash devices, etc., implement algorithms for error correction of encoded data. Algorithms used for error correction operate on data encoded via convolutional codes, e.g., Viterbi decode, and block codes, e.g., Reed-Solomon codes, turbo codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Muller codes, Binary Golay codes, etc.
Algorithms used for error correction may depend on the type of electronic device using the data and its application. For example, NAND flash technology may require high error correction, e.g., 16 bits. Accordingly, a BCH code may be used to correct t-errors in a given data block. The design of the BCH code is influenced by the number of error correction bits required and the data block size.
In general, error correction using BCH codes requires the syndromes to be generated from the encoded data. An error locator polynomial M(x) is calculated from the generated syndromes. The roots of the error locator polynomial M(x) are found in order to determine the location of the error bits.
Unfortunately, finding the roots of the error locator polynomial M(x) is an iterative process, e.g., using Chien's search, and can be very time consuming. The duration of the iterative process depends on the data block size and may take hundreds to thousands of clock cycles to complete.
Generally, one or two bit error conditions have a higher probability distribution in comparison to more than two bit errors. Thus, fast decoding procedures for one or two error bit conditions improves the effective bandwidth of BCH codes.
A hamming code may be used for correcting a single-error, thereby improving the number of clock cycles required. Faster decoding circuits have been developed for two bit errors, as described by Saxena et al., U.S. Pat. No. 5,533,035 and by Kustedjo et al., U.S. Pat. No. 4,360,916.
Unfortunately, the faster two bit error correction described by Saxena et al, and Kustedjo et al., are still iterative. Normally each potential error position is tried until the error is detected and corrected. Thus, the faster two bit error correction, as described by Saxena et al., and Kustedjo et al., while improving the effective bandwidth of BCH codes still require hundreds if not thousands of iterative clock cycles.